1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, particularly, to a method for manufacturing a semiconductor device having a dual damascene wiring structure using an interlayer insulating film which has a low dielectric constant and is formed of an organic insulating film.
2. Description of the Related Art
Miniaturization of a metal wiring is being promoted in an attempt to comply with the demands for the further improvement in the switching speed of a semiconductor device. In addition, miniaturization of the via hole for connecting the adjacent metal wiring layers and the lowering in the dielectric constant of the interlayer insulating film are said to be critical for further improving the switching speed of the semiconductor device.
However, the size that can be obtained by the processing is limited if the processing size is to be miniaturized by simply improving the capability of the lithography technology employed for forming a trench in which the metal wiring is to be buried and for forming a via hole for connecting the adjacent metal wiring layers. In such the situation, the processing with a desired small size is being made difficult. It should also be noted that a hybrid structure including an organic insulating film and an inorganic insulating film is employed as an insulating film formed between the adjacent metal wiring layers, and a laminate structure is employed in the hard mask that is used for performing the dry etching. In addition, a cap insulating film is formed on the metal wiring layer and on the insulating film having a low dielectric constant. As a result, the construction of semiconductor device is made more complex. Under the circumstances, the nonuniformity of the size caused by the fluctuation of the etching rate has come to be attracted attention as a problem to be solved in applying a dry etching to various insulating films.